cmos-ccd 1h delay line for ntsc description the CXL1504M is a delay line used in conjunction with an external low-pass filter. through negative phase input and positive phase output 1h delay time is obtained for ntsc signals. features single 5v power supply 14.3mhz driver low power consumption at 160mw (typ.) built-in peripheral circuits completely adjustment free functions 905.5-bit ccd register clock driver autobias circuit input clamp circuit sample and hold circuit structure cmos-ccd absolute maximum ratings (ta = 25?) supply voltage v dd 6v operating temperature topr ?0 to +60 ? storage temperature tstg ?5 to +150 ? allowable power dissipation p d 500 mw operating voltage range (ta = 25?) supply voltage v dd 5 5% v recommended clock conditions (ta = 25?) input clock amplitude v clk 0.3 to 1.0 vp-p (0.5vp-p typ.) clock frequency f clk 14.318182 mhz input clock waveform sine wave input signal amplitude v sig 560 mvp-p (max.) ?1 e71217a78-ps sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. CXL1504M 20 pin sop (plastic)
? 2 CXL1504M block diagram and pin configuration (top view) 2 3 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 7 1 8 1 9 2 0 i s a b n c i n v d d v s s v g g a o u t v s s v g g b s u b n c n c v d d c l k v s s n c v d d n c v s s b i a s c i r c u i t ( b ) b i a s c i r c u i t ( a ) 4 5 c c d ( 9 0 5 . 5 b i t ) c l o c k d r i v e r o u t p u t c i r c u i t , s / h c i r c u i t p u l s e g e n e r a t i o n c i r c u i t 1 1 6 f 1 f 2 f s / h a u t o b i a s c i r c u i t pin description pin no. symbol i/o description impedance [ ] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 is ab nc in v dd v ss v gg a out v ss v gg b v ss nc v dd nc v ss clk v dd nc nc sub o o i o o o i ccd bias dc output autobias dc output signal input (negative phase signal) 5v power supply (for clock driver) gnd gate bias (a) dc output signal output (positive phase signal) gnd gate bias (b) dc output gnd 5v power supply (for analog system) gnd clock input 5v power supply (for digital system) gnd 600 to 2k 2k to 20k > 100k (at no clamp) 2k to 10k 40 to 500 2k to 10k 4k to 50k
? 3 CXL1504M electrical characteristics (ta = 25 c, v dd = 5v, f clk = 14.318182mhz, v clk = 500mvp-p, sine wave) see the electrical characteristics test circuits. item symbol test conditions sw conditions min. typ. max. unit note (note 1) bias conditions v bias 1 [v] 1 2 3 4 b b c c a d a a b a a b a a a a a a b a a a b c d d e 200khz, 500mvp-p, sine wave 200khz ? ? 3.58mhz, 150mvp-p, sine wave 5-staircase wave (see note 5) 5-staircase wave (see note 5) no signal input 50% white video signal (see note 7) i dd gl fr dg dp cp s/n supply current low frequency gain frequency response differential gain differential phase s/h pulse coupling s/n ratio ? ? notes 1) v in is defined as follows. v in is the input signal clamp level, it clamps the video signal sync tip level. c x l 1 5 0 4 i n p u t ( i n ) c l a m p l e v e l v i n 4 n e g a t i v e p h a s e s i g n a l i n p u t v in is the pin voltage for pin 4 at no-input signal. testing is executed with a voltmeter under the follwing sw conditions. as v in varies with each ic, they are all subject to testing. 2) i dd is the ic supply current value during clock and signal input. 3) gl is the out pin output gain when a 500mvp-p, 200khz sine wave is input to in pin. gl = 20 log [db] sw conditions item v in test point v1 1 2 b 3 a 4 v in ?0.2 v in ma db db % degree mvp-p db 42 ?.0 0 7 7 350 32 ?.0 ?.3 3 3 200 56 20 ?.0 ?.5 0 0 54 2 3 4 5 5 6 7 out pin output voltage [mvp-p] 500 [mvp-p]
? 4 CXL1504M 4) indicates the dissipation at 3.58mhz in relation to 200khz. from the output voltage at out pin when a 150mvp-p, 200khz sine wave is fed to in pin, and from the output voltage at out pin when a 150mvp-p, 3.58mhz sine wave is fed to same, calculation is made according to the following formula. the input part bias is tested at v in ?0.2v. fr = 20 log [db] 5) the differential gain (dg) and the differential phase (dp), when the 5-staircase wave in the figure. below is input are tested at the vector scope. out pin output voltage (3.58mhz) [mvp-p] out pin output voltage (200khz) [mvp-p] 5 0 0 m v 1 h 6 3 . 5 6 s 1 4 3 m v 3 5 7 m v 1 4 3 m v in pin input waveform is the inverted waveform in the figure above 6) the internal clock component to the output signal during no-signal input and the leakage of that high harmonic component are tested. the input part bias is tested at v in v. t e s t v a l u e ( m v p - p ) 7) s/n ratio during 50% white video signal input shown in figure. below is tested at a video noise meter, in bpf 100khz to 4mhz, sub carrier trap mode. 3 2 1 m v 1 h 6 3 . 5 6 s 1 4 3 m v 1 7 8 m v in pin input waveform is the inverted waveform in the figure above 0 . 3 v p - p t o 1 . 0 v p - p ( 0 . 5 v p - p t y p . ) 4 f s c ( 1 4 . 3 1 8 1 8 2 m h z ) s i n e w a v e clock
? 5 CXL1504M electrical characteristics test circuit l p f 3 b p f 3 a b c d 1 m s w 3 a b v 1 1 a b s w 2 1 s w 1 2 0 0 k h z 5 0 0 m v p - p s i n e w a v e 2 0 0 k h z 1 5 0 m v p - p s i n e w a v e 3 . 5 8 m h z 1 5 0 m v p - p s i n e w a v e 5 0 % w h i t e v i d e o s i g n a l 5 - s t a i r c a s e w a v e a b c d s w 4 0 6 m 1 4 . 3 m f r e q u e n c y [ h z ] 5 0 3 0 [ d b ] n o t e 1 ) l p f f r e q u e n c y r e s p o n s e 0 6 m 1 4 . 3 m f r e q u e n c y [ h z ] 5 0 3 0 [ d b ] n o t e 2 ) b p f f r e q u e n c y r e s p o n s e 2 0 0 v b i a s 1 1 3 . 3 0 . 1 c l k 4 f s c ( 1 4 . 3 1 8 1 8 2 m h z ) 0 . 5 v p - p s i n e w a v e 1 0 . 0 1 3 . 3 1 . 2 k 5 v 1 1 0 . 0 1 3 . 3 0 . 0 1 2 4 6 7 8 9 1 0 1 4 1 5 1 7 1 8 1 9 2 0 1 5 1 6 3 1 1 1 2 1 3 e 9 v n o t e 1 ) n o t e 2 ) o s c i l l o s c o p e s p e c t r u m a n a l y z e r v e c t o r s c o p e n o i s e m e t e r o s c i l l o - s c o p e i s a b n c i n v d d v s s v g g a o u t v s s v g g b s u b n c n c v d d c l k v s s n c v d d n c v s s c x l 1 5 0 4 m 5 1 k
? 6 CXL1504M application circuit 1 3 . 3 0 . 1 1 4 . 3 1 8 1 8 2 m h z 0 . 5 v p - p s i n e w a v e 1 0 . 0 1 3 . 3 1 . 2 k 5 v 9 v t r a n s i s t o r u s e d p n p . 2 s a 1 1 7 5 s i g n a l o u t p u t ( p o s i t i v e p h a s e s i g n a l ) 1 m 1 s i g n a l i n p u t ( n e g a t i v e p h a s e s i g n a l ) 1 1 0 . 0 1 3 . 3 0 . 0 1 2 4 6 7 8 9 1 0 1 4 1 5 1 7 1 8 1 9 2 0 1 5 1 6 3 1 1 1 2 1 3 c x l 1 5 0 4 m application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility fo r any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same .
? 7 CXL1504M 0 1 2 3 s u p p l y v o l t a g e [ v ] f r e q u e n c y r e s p o n s e [ d b ] f r e q u e n c y r e s p o n s e v s . s u p p l y v o l t a g e 4 . 7 5 5 . 0 5 . 2 5 4 0 3 0 s u p p l y c u r r e n t [ m a ] 2 0 s u p p l y c u r r e n t v s . s u p p l y v o l t a g e s u p p l y v o l t a g e [ v ] 4 . 7 5 5 . 0 5 . 2 5 0 2 0 4 0 6 0 a m b i e n t t e m p e r a t u r e [ c ] l o w f r e q u e n c y g a i n v s . a m b i e n t t e m p e r a t u r e 1 2 3 4 5 l o w f r e q u e n c y g a i n [ d b ] 0 2 0 4 0 6 0 a m b i e n t t e m p e r a t u r e [ c ] f r e q u e n c y r e s p o n s e v s . a m b i e n t t e m p e r a t u r e 0 1 2 3 f r e q u e n c y r e s p o n s e [ d b ] l o w f r e q u e n c y g a i n v s . s u p p l y v o l t a g e 1 2 3 4 5 4 . 7 5 5 . 0 5 . 2 5 s u p p l y v o l t a g e [ v ] l o w f r e q u e n c y g a i n [ d b ] 1 0 8 6 4 d i f f e r e n t i a l g a i n [ % ] d i f f e r e n t i a l g a i n v s . s u p p l y v o l t a g e 4 . 7 5 5 . 0 5 . 2 5 s u p p l y v o l t a g e [ v ] 2 0 example of representative characteristics
? 8 CXL1504M a m b i e n t t e m p e r a t u r e [ c ] s u p p l y c u r r e n t [ m a ] 0 s u p p l y c u r r e n t v s . a m b i e n t t e m p e r a t u r e 4 0 2 0 2 0 4 0 6 0 3 0 f r e q u e n c y r e s p o n s e 0 2 4 6 1 0 k g a i n [ d b ] 1 0 0 k 1 m 8 f r e q u e n c y [ h z ] 1 0 m 8 6 4 0 2 0 a m b i e n t t e m p e r a t u r e [ c ] d i f f e r e n t i a l g a i n [ % ] d i f f e r e n t i c a l g a i n v s . a m b i e n t t e m p e r a t u r e 1 0 4 0 6 0 3 0
? 9 CXL1504M package outline unit: mm s o n y c o d e e i a j c o d e j e d e c c o d e s o p - 2 0 p - l 0 1 s o p 0 2 0 - p - 0 3 0 0 p a c k a g e s t r u c t u r e p a c k a g e m a t e r i a l l e a d t r e a t m e n t l e a d m a t e r i a l p a c k a g e m a s s c o p p e r a l l o y s o l d e r p l a t i n g e p o x y r e s i n 0 . 3 g 2 0 p i n s o p ( p l a s t i c ) 1 2 . 4 5 0 . 1 + 0 . 4 2 0 1 1 0 . 4 5 0 . 1 1 . 2 7 1 0 1 5 . 3 0 . 1 + 0 . 3 7 . 9 0 . 4 6 . 9 0 . 2 0 . 0 5 + 0 . 1 0 . 5 0 . 2 0 . 1 0 . 0 5 + 0 . 2 1 . 8 5 0 . 1 5 + 0 . 4 0 . 1 5 0 . 2 4 m
|
